The 0.1‑Microvolt Challenge: Cloning the High‑Sensitivity Detection Probe of the HP 437B Power Meter.
Author
lzm
Date Published
Schottky‑diode square‑law detection principle – a high‑sensitivity RF power probe circuit (home‑built replacement probe) designed specifically for the HP 437B power meter. The original designer, Joshua (DL3JOP), referenced designs by SM0XGY and HB9FSX. From the schematic, the core design logic is tightly linked to three engineering philosophies: thermal isolation, high‑impedance buffering, and auto‑zeroing.

1. Core Architecture and Signal Chain
RF detection stage (core sensor)
D1 (BAT62‑03W): This is the heart of the entire circuit. The BAT62 is a silicon Schottky diode, operated here at zero bias or in the square‑law region (typically suitable for input powers from –20 dBm to 0 dBm). It rectifies the incoming RF signal into a DC voltage proportional to the input power (Vout = k·Pin).
Critical matching: R7 (FB – ferrite bead), R8 (15 Ω), and C6/C7 (100 nF) form the RF input matching and filtering network, ensuring optimum RF power transfer to the diode while filtering out residual high‑frequency carrier components.

Active buffer and amplification stage (signal conditioning)
U1 (JFE2140): This is a dual, low‑noise JFET, not an ordinary op‑amp. It is used here as a high‑impedance voltage follower (buffer).
Why not a standard op‑amp? The output impedance of a Schottky diode at zero bias is extremely high (up to several megohms), and the output current is minuscule. If connected directly to an ADC or meter, the signal would be severely loaded. The JFE2140 features tera‑ohm (TΩ) input impedance and pA‑level gate leakage current, allowing it to perfectly “pick up” the weak voltage from the detector diode without introducing additional loading or error.

Power supply and filtering network (ensuring cleanliness)
R13 (FB – ferrite bead): Placed in series with the power rail to suppress high‑frequency noise (e.g., DC‑DC ripple or ambient EMI) from entering the sensitive analogue front‑end.
Capacitor bank (C3 22 µF, C4 220 µF, C5 3.3 µF, C9/C10 100 nF): A combination of “large capacitors for low‑frequency stability and small capacitors for high‑frequency bypass” ensures that the supply to the JFET and bias circuitry is extremely smooth, preventing power‑supply noise from swamping the weak detected signal.

2. Special Design Details and Engineering Philosophy
“Thermally separated” – the key to success
This annotation on the schematic means that, in the PCB layout, the detector diode D1 must be physically separated from heat‑generating components (such as linear regulators, power resistor R10 3.3 kΩ, and R11/R12 270 Ω).
Reason: The forward voltage (Vf) of a Schottky diode has a temperature coefficient of about –2 mV/°C. If soldering heat causes the diode’s temperature to drift, the DC output will “wander”, leading to serious inaccuracies in the detected power reading. Thermal isolation is a prerequisite for zero‑point stability.

“AUTOZERO_PAD” and “COMPENSATION TBD”
AUTOZERO_PAD: This pad most likely connects to the second JFET channel of the JFE2140 or to an external op‑amp, forming a sample‑and‑hold or auto‑zero circuit. Because diode detection has an inherent DC offset (microvolt‑level output even with zero input), precision power meters like the HP 437B use this function to short the input and zero the reading before measurement.
COMPENSATION TBD (To Be Determined): This RC network is intended for frequency compensation or phase‑margin adjustment. Since JFET amplifiers are prone to oscillation due to capacitive loads (e.g., long coaxial cables), the reserved network of R14 (1 kΩ) and C10 (100 nF) must be “tuned by trial soldering” based on the actual PCB parasitic capacitance – a classic example of the “black magic” debugging mindset in RF analogue circuitry.

Guard ring and reference grounds (GUARDGNDPAD & PGND)
The schematic notes GUARD_GND_PAD (guard ring) and PGND (power ground / sense ground separation). In pA‑level current circuits, the guard ring surrounds the high‑impedance input pins (the gate of the JFE2140) to absorb surface leakage currents on the PCB, preventing them from affecting measurement accuracy.